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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_scu_gic.html">XScuGic</a></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:ga2a4ba236ff7bfeab20b5ca81082f2b13"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga2a4ba236ff7bfeab20b5ca81082f2b13">XScuGic_CPUWriteReg</a>(InstancePtr,  RegOffset,  Data)</td></tr>
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<tr class="memitem:ga2f3bba7c5247812158ef4fde7a0e7dfe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga2f3bba7c5247812158ef4fde7a0e7dfe">XScuGic_CPUReadReg</a>(InstancePtr,  RegOffset)&#160;&#160;&#160;(<a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>(((InstancePtr)-&gt;Config-&gt;CpuBaseAddress), (RegOffset)))</td></tr>
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<tr class="memitem:ga22e9f81ed00f7cc39df1c6e76988fdb1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>(InstancePtr,  RegOffset,  Data)</td></tr>
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<tr class="memitem:ga3d639fe1851f9d833367fb4322390eeb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga3d639fe1851f9d833367fb4322390eeb">XScuGic_DistReadReg</a>(InstancePtr,  RegOffset)&#160;&#160;&#160;(<a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>(((InstancePtr)-&gt;Config-&gt;DistBaseAddress), (RegOffset)))</td></tr>
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Functions</h2></td></tr>
<tr class="memitem:gaf8e0bfe31c0fa2ca654c36715a3c13f8"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#gaf8e0bfe31c0fa2ca654c36715a3c13f8">XScuGic_CfgInitialize</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, <a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> *ConfigPtr, u32 EffectiveAddr)</td></tr>
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<tr class="memitem:ga48f9dd531aa861a74e6bd627943573ea"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga48f9dd531aa861a74e6bd627943573ea">XScuGic_Connect</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id, Xil_InterruptHandler Handler, void *CallBackRef)</td></tr>
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<tr class="memitem:gad162acedbbd41fd890fc7f2225ed480b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#gad162acedbbd41fd890fc7f2225ed480b">XScuGic_Disconnect</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id)</td></tr>
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<tr class="memitem:gac965b9e3ae7668a92cf07a65bde142cc"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#gac965b9e3ae7668a92cf07a65bde142cc">XScuGic_Enable</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id)</td></tr>
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<tr class="memitem:gaafd153e16238a1189c513846675e096a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#gaafd153e16238a1189c513846675e096a">XScuGic_Disable</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id)</td></tr>
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<tr class="memitem:gad71d2f581bdc46d89f38fced53e506bf"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#gad71d2f581bdc46d89f38fced53e506bf">XScuGic_SoftwareIntr</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id, u32 Cpu_Id)</td></tr>
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<tr class="memitem:ga79abd6248cb578142e9c475f20dbeb06"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id, u8 Priority, u8 Trigger)</td></tr>
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<tr class="memitem:ga6ed162180ffb45b082c2fbe23951ba13"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga6ed162180ffb45b082c2fbe23951ba13">XScuGic_GetPriorityTriggerType</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id, u8 *Priority, u8 *Trigger)</td></tr>
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<tr class="memitem:ga40ef6d42e9520bb550163c3afd598980"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga40ef6d42e9520bb550163c3afd598980">XScuGic_InterruptMaptoCpu</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u8 Cpu_Id, u32 Int_Id)</td></tr>
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<tr class="memitem:gab2c0554b809121cc91a96fcd8c749c25"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#gab2c0554b809121cc91a96fcd8c749c25">XScuGic_LookupConfig</a> (u16 DeviceId)</td></tr>
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<tr class="memitem:gaa26a952ecd376be0bc3d8433023d1364"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#gaa26a952ecd376be0bc3d8433023d1364">XScuGic_InterruptHandler</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr)</td></tr>
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<tr class="memitem:ga081a9a62546b413d94e609894282a575"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga081a9a62546b413d94e609894282a575">XScuGic_SelfTest</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr)</td></tr>
<tr class="separator:ga081a9a62546b413d94e609894282a575"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2cbf5d5ac5273e00c0b16bd33ad0707f"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga2cbf5d5ac5273e00c0b16bd33ad0707f">XScuGic_DeviceInitialize</a> (u32 DeviceId)</td></tr>
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<tr class="memitem:ga96bfe161e3b4e401f76f2b35df9fab86"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga96bfe161e3b4e401f76f2b35df9fab86">XScuGic_DeviceInterruptHandler</a> (void *DeviceId)</td></tr>
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<tr class="memitem:ga73f026dbb3a8f29b830fb0a64a42c4bf"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga73f026dbb3a8f29b830fb0a64a42c4bf">XScuGic_RegisterHandler</a> (u32 BaseAddress, s32 InterruptID, Xil_InterruptHandler IntrHandler, void *CallBackRef)</td></tr>
<tr class="separator:ga73f026dbb3a8f29b830fb0a64a42c4bf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf58a00ee3c052d8aec17b179c86388c7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#gaf58a00ee3c052d8aec17b179c86388c7">XScuGic_SetPriTrigTypeByDistAddr</a> (u32 DistBaseAddress, u32 Int_Id, u8 Priority, u8 Trigger)</td></tr>
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<tr class="memitem:ga0c6a61acf2d5d030542c788a9aa42004"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga0c6a61acf2d5d030542c788a9aa42004">XScuGic_GetPriTrigTypeByDistAddr</a> (u32 DistBaseAddress, u32 Int_Id, u8 *Priority, u8 *Trigger)</td></tr>
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Variables</h2></td></tr>
<tr class="memitem:gaca56d0e0512f7fb4430977d6b6d598a9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#gaca56d0e0512f7fb4430977d6b6d598a9">XScuGic_ConfigTable</a> [XPAR_XSCUGIC_NUM_INSTANCES]</td></tr>
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<tr class="memitem:gaca56d0e0512f7fb4430977d6b6d598a9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#gaca56d0e0512f7fb4430977d6b6d598a9">XScuGic_ConfigTable</a> [XPAR_XSCUGIC_NUM_INSTANCES]</td></tr>
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<tr class="memitem:ga08dd4912e27f17887b05670c3b5576b3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga08dd4912e27f17887b05670c3b5576b3">XScuGic_ConfigTable</a> [XPAR_SCUGIC_NUM_INSTANCES]</td></tr>
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CPU Interface Register Map</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpae7a7a841f30e81a731ad01209d34189"></a>Define the offsets from the base address for all CPU registers of the interrupt controller, some registers may be reserved in the hardware device. </p>
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<tr class="memitem:ga8ca0e14be574b074b47ef33108794ca1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga8ca0e14be574b074b47ef33108794ca1">XSCUGIC_ALIAS_BIN_PT_OFFSET</a>&#160;&#160;&#160;0x0000001CU</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="gad9945cea79930d883f977fc97e1aa292"></a>
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          <td class="memname">#define XSCUGIC_ACK_INTID_MASK&#160;&#160;&#160;0x000003FFU</td>
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<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Interrupt ID. </p>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#ga96bfe161e3b4e401f76f2b35df9fab86">XScuGic_DeviceInterruptHandler()</a>, and <a class="el" href="group__scugic__v3__1.html#gaa26a952ecd376be0bc3d8433023d1364">XScuGic_InterruptHandler()</a>.</p>

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</div>
<a class="anchor" id="ga8ffa809cf8e6e237833431b9e28e74b6"></a>
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          <td class="memname">#define XSCUGIC_ACTIVE_MASK&#160;&#160;&#160;0x00000001U</td>
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<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Each bit corresponds to an INT_ID. </p>

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<a class="anchor" id="ga522b8af56f229548a2360bdbedd7a6f3"></a>
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          <td class="memname">#define XSCUGIC_ACTIVE_OFFSET&#160;&#160;&#160;0x00000300U</td>
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<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Active Status Register. </p>

</div>
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<a class="anchor" id="ga0d4a040ef70e7a3c49d3175dbb1eb381"></a>
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          <td class="memname">#define XSCUGIC_AHB_CONFIG_OFFSET&#160;&#160;&#160;0x00000D80U</td>
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<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>AHB Configuration Register. </p>

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<a class="anchor" id="ga3b4028834925dd0ed1a6175492d8ae89"></a>
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          <td class="memname">#define XSCUGIC_AHB_END_MASK&#160;&#160;&#160;0x00000004U</td>
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<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>0-GIC uses little Endian, 1-GIC uses Big Endian </p>

</div>
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<a class="anchor" id="gaa9d9d58262a639eb2a8858e2856b277d"></a>
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          <td class="memname">#define XSCUGIC_AHB_ENDOVR_MASK&#160;&#160;&#160;0x00000002U</td>
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<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>0-Uses CFGBIGEND control, 1-use the AHB_END bit </p>

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<a class="anchor" id="ga786c66ef9c8619b0a36ae25e85ea58e5"></a>
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          <td class="memname">#define XSCUGIC_AHB_TIE_OFF_MASK&#160;&#160;&#160;0x00000001U</td>
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<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>State of CFGBIGEND. </p>

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<a class="anchor" id="ga8ca0e14be574b074b47ef33108794ca1"></a>
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          <td class="memname">#define XSCUGIC_ALIAS_BIN_PT_OFFSET&#160;&#160;&#160;0x0000001CU</td>
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      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Aliased non-Secure Binary Point Register. </p>
<p>0x00000020 to 0x00000FBC are reserved and should not be read or written to. </p>

</div>
</div>
<a class="anchor" id="gabb83f3fd04a69ac1f7ace985db677e63"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_BIN_PT_MASK&#160;&#160;&#160;0x00000007U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Binary point mask value Value Secure Non-secure b000 0xFE 0xFF b001 0xFC 0xFE b010 0xF8 0xFC b011 0xF0 0xF8 b100 0xE0 0xF0 b101 0xC0 0xE0 b110 0x80 0xC0 b111 0x00 0x80. </p>

</div>
</div>
<a class="anchor" id="gab0aa4aa9a2e2b9af2b654967f387dd2c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_BIN_PT_OFFSET&#160;&#160;&#160;0x00000008U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Binary Point Register. </p>

</div>
</div>
<a class="anchor" id="ga24146dc008dc9a9d8b76fb802bf843ab"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_CNTR_ACKCTL_MASK&#160;&#160;&#160;0x00000004U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Ack control for secure or non secure. </p>

</div>
</div>
<a class="anchor" id="ga95e109eaaa18f39f1525967987bb5167"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_CNTR_EN_NS_MASK&#160;&#160;&#160;0x00000002U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Non Secure enable. </p>

</div>
</div>
<a class="anchor" id="gaaea986d126fc3cf6efc9cdc86e347475"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_CNTR_EN_S_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Secure enable, 0=Disabled, 1=Enabled. </p>

</div>
</div>
<a class="anchor" id="gaa696959041b1e0b4c5008c9fbf25a8b2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_CNTR_FIQEN_MASK&#160;&#160;&#160;0x00000008U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Use nFIQ_C for secure interrupts, 0= use IRQ for both, 1=Use FIQ for secure, IRQ for non. </p>

</div>
</div>
<a class="anchor" id="gab30530d436aee9b8fe1df9e0ddc9ac90"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_CNTR_SBPR_MASK&#160;&#160;&#160;0x00000010U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Secure Binary Pointer, 0=separate registers, 1=both use bin_pt_s. </p>

</div>
</div>
<a class="anchor" id="gadc15f5222681d55b9c1d391b067d37fa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_CONTROL_OFFSET&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>CPU Interface Control Register. </p>

</div>
</div>
<a class="anchor" id="ga21918105af9b486b28a8581c2caac127"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_CPU_NUM_MASK&#160;&#160;&#160;0x000000E0U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Number of CPU Interfaces. </p>

</div>
</div>
<a class="anchor" id="ga924ad35e75dc4788443bee4dc2d1e61e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_CPU_PRIOR_OFFSET&#160;&#160;&#160;0x00000004U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Priority Mask Reg. </p>

</div>
</div>
<a class="anchor" id="ga3ea14a0a5360cd67164dc801ef1d7e3d"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_CPUID_MASK&#160;&#160;&#160;0x00000C00U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>CPU ID. </p>

</div>
</div>
<a class="anchor" id="ga2f3bba7c5247812158ef4fde7a0e7dfe"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XScuGic_CPUReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(<a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>(((InstancePtr)-&gt;Config-&gt;CpuBaseAddress), (RegOffset)))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic_8h.html">xscugic.h</a>&gt;</code></p>

<p>Read the given CPU Interface register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the instance to be worked on. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to be read</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__scugic__v3__1.html#ga2f3bba7c5247812158ef4fde7a0e7dfe" title="Read the given CPU Interface register. ">XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#gaa26a952ecd376be0bc3d8433023d1364">XScuGic_InterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ga2a4ba236ff7bfeab20b5ca81082f2b13"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XScuGic_CPUWriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic_8h.html">xscugic.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a>(((InstancePtr)-&gt;Config-&gt;CpuBaseAddress), (RegOffset), \</div>
<div class="line">                                        ((u32)(Data))))</div>
<div class="ttc" id="xscugic__hw_8h_html_a01c0f85e48858531c313ce22cbfd2dfa"><div class="ttname"><a href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a></div><div class="ttdeci">#define XScuGic_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">Write the given Intc register. </div><div class="ttdef"><b>Definition:</b> xscugic_hw.h:624</div></div>
</div><!-- fragment -->
<p>Write the given CPU Interface register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the instance to be worked on. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to be written </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the register</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__scugic__v3__1.html#ga2a4ba236ff7bfeab20b5ca81082f2b13" title="Write the given CPU Interface register. ">XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#gaa26a952ecd376be0bc3d8433023d1364">XScuGic_InterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ga7a61a9bf8e0b229925a5ddbf763b414b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_DISABLE_OFFSET&#160;&#160;&#160;0x00000180U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Enable Clear Register. </p>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#gaafd153e16238a1189c513846675e096a">XScuGic_Disable()</a>, and <a class="el" href="group__scugic__v3__1.html#gad162acedbbd41fd890fc7f2225ed480b">XScuGic_Disconnect()</a>.</p>

</div>
</div>
<a class="anchor" id="ga94cd5e2c3a1ab5b6c282d76bead5d616"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_DIST_EN_OFFSET&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Distributor Enable Register. </p>

</div>
</div>
<a class="anchor" id="gaff73afc08cc167202d5aac6661ae6a1e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_DIST_IDENT_OFFSET&#160;&#160;&#160;0x00000008U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Implementor ID Register. </p>

</div>
</div>
<a class="anchor" id="ga3d639fe1851f9d833367fb4322390eeb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XScuGic_DistReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(<a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>(((InstancePtr)-&gt;Config-&gt;DistBaseAddress), (RegOffset)))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic_8h.html">xscugic.h</a>&gt;</code></p>

<p>Read the given Distributor Interface register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the instance to be worked on. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to be read</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__scugic__v3__1.html#ga3d639fe1851f9d833367fb4322390eeb" title="Read the given Distributor Interface register. ">XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#ga6ed162180ffb45b082c2fbe23951ba13">XScuGic_GetPriorityTriggerType()</a>, <a class="el" href="group__scugic__v3__1.html#ga40ef6d42e9520bb550163c3afd598980">XScuGic_InterruptMaptoCpu()</a>, <a class="el" href="group__scugic__v3__1.html#ga081a9a62546b413d94e609894282a575">XScuGic_SelfTest()</a>, and <a class="el" href="group__scugic__v3__1.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType()</a>.</p>

</div>
</div>
<a class="anchor" id="ga22e9f81ed00f7cc39df1c6e76988fdb1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XScuGic_DistWriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic_8h.html">xscugic.h</a>&gt;</code></p>
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a>(((InstancePtr)-&gt;Config-&gt;DistBaseAddress), (RegOffset), \</div>
<div class="line">                                        ((u32)(Data))))</div>
<div class="ttc" id="xscugic__hw_8h_html_a01c0f85e48858531c313ce22cbfd2dfa"><div class="ttname"><a href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a></div><div class="ttdeci">#define XScuGic_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">Write the given Intc register. </div><div class="ttdef"><b>Definition:</b> xscugic_hw.h:624</div></div>
</div><!-- fragment -->
<p>Write the given Distributor Interface register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the instance to be worked on. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to be written </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the register</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__scugic__v3__1.html#ga22e9f81ed00f7cc39df1c6e76988fdb1" title="Write the given Distributor Interface register. ">XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#gaafd153e16238a1189c513846675e096a">XScuGic_Disable()</a>, <a class="el" href="group__scugic__v3__1.html#gad162acedbbd41fd890fc7f2225ed480b">XScuGic_Disconnect()</a>, <a class="el" href="group__scugic__v3__1.html#gac965b9e3ae7668a92cf07a65bde142cc">XScuGic_Enable()</a>, <a class="el" href="group__scugic__v3__1.html#ga40ef6d42e9520bb550163c3afd598980">XScuGic_InterruptMaptoCpu()</a>, <a class="el" href="group__scugic__v3__1.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType()</a>, and <a class="el" href="group__scugic__v3__1.html#gad71d2f581bdc46d89f38fced53e506bf">XScuGic_SoftwareIntr()</a>.</p>

</div>
</div>
<a class="anchor" id="gaad0bd2ae20c2b47d8c7aaea2a78f5199"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_DOMAIN_MASK&#160;&#160;&#160;0x00000400U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Number os Security domains. </p>

</div>
</div>
<a class="anchor" id="gabd696b30c6257dea212cb9925ba73796"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_EN_INT_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Interrupt In Enable. </p>

</div>
</div>
<a class="anchor" id="ga7e39be0cb9e08f4c9231f76e685a76cc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_ENABLE_SET_OFFSET&#160;&#160;&#160;0x00000100U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Enable Set Register. </p>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#gac965b9e3ae7668a92cf07a65bde142cc">XScuGic_Enable()</a>.</p>

</div>
</div>
<a class="anchor" id="gad50524a3c9f6edaac90d6fa47907ec10"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_EOI_INTID_MASK&#160;&#160;&#160;0x000003FFU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Interrupt ID. </p>

</div>
</div>
<a class="anchor" id="gaa65c329712b1a7f3ab12b0bf4ada058d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_EOI_OFFSET&#160;&#160;&#160;0x00000010U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>End of Interrupt Reg. </p>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#ga96bfe161e3b4e401f76f2b35df9fab86">XScuGic_DeviceInterruptHandler()</a>, and <a class="el" href="group__scugic__v3__1.html#gaa26a952ecd376be0bc3d8433023d1364">XScuGic_InterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="gaa8f4426fddda8466c267b661457dd54e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_HI_PEND_OFFSET&#160;&#160;&#160;0x00000018U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Highest Pending Interrupt Register. </p>

</div>
</div>
<a class="anchor" id="ga80f182c20ecfcc115bca1ac7aae08889"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_IC_TYPE_OFFSET&#160;&#160;&#160;0x00000004U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Interrupt Controller Type Register. </p>

</div>
</div>
<a class="anchor" id="gab972b346f99c89c1913e6e49edc6fb0d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_IMPL_MASK&#160;&#160;&#160;0x00000FFFU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Implementor. </p>

</div>
</div>
<a class="anchor" id="ga5f1418c8f0e05b7f928c2fff42b4514d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_INT_ACK_OFFSET&#160;&#160;&#160;0x0000000CU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Interrupt ACK Reg. </p>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#ga96bfe161e3b4e401f76f2b35df9fab86">XScuGic_DeviceInterruptHandler()</a>, and <a class="el" href="group__scugic__v3__1.html#gaa26a952ecd376be0bc3d8433023d1364">XScuGic_InterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ga8c3e4a0e11aeeb05a7425826893a48b5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_INT_CFG_OFFSET&#160;&#160;&#160;0x00000C00U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Interrupt Configuration Register 0xC00-0xCFC. </p>

</div>
</div>
<a class="anchor" id="ga53b866f6da52f01e4e230217b92203e1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_INT_CLR_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Each bit corresponds to an INT_ID. </p>

</div>
</div>
<a class="anchor" id="ga235b4d8d83653aae756d0377f6d42793"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_INT_EN_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Each bit corresponds to an INT_ID. </p>

</div>
</div>
<a class="anchor" id="gadd615bcd7723580422f99170f7beff31"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_INT_NS_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Each bit corresponds to an INT_ID. </p>

</div>
</div>
<a class="anchor" id="ga63c9b51176e1db04adbbfa91b517d9a1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_LSPI_MASK&#160;&#160;&#160;0x0000F800U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Number of Lockable Shared Peripheral Interrupts. </p>

</div>
</div>
<a class="anchor" id="ga5e47c517a580a243cde47a69d1fe6d50"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_NUM_INT_MASK&#160;&#160;&#160;0x0000001FU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Number of Interrupt IDs. </p>

</div>
</div>
<a class="anchor" id="ga41becddbff3dcc589f4c9d70d0177ff6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PCELLID_OFFSET&#160;&#160;&#160;0x00000FF0U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Pcell ID Register. </p>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#ga081a9a62546b413d94e609894282a575">XScuGic_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="gac000c78a5731608de6ea4951fff8b7a5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PEND_CLR_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Each bit corresponds to an INT_ID. </p>

</div>
</div>
<a class="anchor" id="ga1aea23f3bd1941b93443e441bd1e8e58"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PEND_INTID_MASK&#160;&#160;&#160;0x000003FFU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Pending Interrupt ID. </p>

</div>
</div>
<a class="anchor" id="gaf9f9e786eda7eaa92e2a2661b6ff194c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PEND_SET_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Each bit corresponds to an INT_ID. </p>

</div>
</div>
<a class="anchor" id="ga3bd893d8bffa293ebf525ff6fc580f82"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PENDING_CLR_OFFSET&#160;&#160;&#160;0x00000280U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Pending Clear Register. </p>

</div>
</div>
<a class="anchor" id="gadf9985097ea7d040ad1eb0d1c45ade3f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PENDING_SET_OFFSET&#160;&#160;&#160;0x00000200U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Pending Set Register. </p>

</div>
</div>
<a class="anchor" id="gaa933fc8e5812dcef2571db933c761d10"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PERPHID_OFFSET&#160;&#160;&#160;0x00000FD0U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Peripheral ID Reg. </p>

</div>
</div>
<a class="anchor" id="gab0d1549e1fdc4ee0efda5b9a7d19f1c9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C00_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="gaa6af05ff49c40b1f95ddef70720c661d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C01_MASK&#160;&#160;&#160;0x00000002U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga841e2da3b34252affcbe1ae420dee5cd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C02_MASK&#160;&#160;&#160;0x00000004U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga1227f27b3f3566c377741ed4500864eb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C03_MASK&#160;&#160;&#160;0x00000008U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="gafb35a04b39200dc2531978c5b819a05f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C04_MASK&#160;&#160;&#160;0x00000010U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="gaddc4c3db586fa77620204fc196c79196"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C05_MASK&#160;&#160;&#160;0x00000020U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="gab4746833af92bb2cd60f47c5aef3c412"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C06_MASK&#160;&#160;&#160;0x00000040U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="gac9103c688cb9f66402d43acdce1ec2d4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C07_MASK&#160;&#160;&#160;0x00000080U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga98cf40b1bb6de7edfe1034883780eb51"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C08_MASK&#160;&#160;&#160;0x00000100U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga5a79ff73cc31e2233f58a682a9421c5d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C09_MASK&#160;&#160;&#160;0x00000200U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga7a0c40850819f2d48d9ccaa274cd4881"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C10_MASK&#160;&#160;&#160;0x00000400U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga8318aad85340f5318de41b98da04100c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C11_MASK&#160;&#160;&#160;0x00000800U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="gabd6aceee4c3c462bc1a9f95495d17181"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C12_MASK&#160;&#160;&#160;0x00001000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="gacc7fa22af93b8377b1f757d83a1a47a4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C13_MASK&#160;&#160;&#160;0x00002000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga6797b4c956ee74df8c35314ce817cc32"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C14_MASK&#160;&#160;&#160;0x00004000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga7fb6f58522fbce60a5d8e51ade739208"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C15_MASK&#160;&#160;&#160;0x00008000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga5b0239e9c600cc249f62309ca6ea7904"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_STAT_OFFSET&#160;&#160;&#160;0x00000D00U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>PPI Status Register. </p>

</div>
</div>
<a class="anchor" id="gaf56426a8af8b676cb9184cf2196b6bf4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PRIORITY_MASK&#160;&#160;&#160;0x000000FFU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Each Byte corresponds to an INT_ID. </p>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#ga6ed162180ffb45b082c2fbe23951ba13">XScuGic_GetPriorityTriggerType()</a>, <a class="el" href="group__scugic__v3__1.html#ga0c6a61acf2d5d030542c788a9aa42004">XScuGic_GetPriTrigTypeByDistAddr()</a>, <a class="el" href="group__scugic__v3__1.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType()</a>, and <a class="el" href="group__scugic__v3__1.html#gaf58a00ee3c052d8aec17b179c86388c7">XScuGic_SetPriTrigTypeByDistAddr()</a>.</p>

</div>
</div>
<a class="anchor" id="ga5c2deb04ec9dad4c61b564f53b246ec0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PRIORITY_MAX&#160;&#160;&#160;0x000000FFU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Highest value of a priority actually the lowest priority. </p>

</div>
</div>
<a class="anchor" id="ga4e103b71357ac53c890d8aebd3b80997"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PRIORITY_OFFSET&#160;&#160;&#160;0x00000400U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Priority Level Register. </p>

</div>
</div>
<a class="anchor" id="ga0e4e42f499ef03373095daf342ffa988"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_REV_MASK&#160;&#160;&#160;0x00FFF000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Revision Number. </p>

</div>
</div>
<a class="anchor" id="ga9032b8ad311f376fd5d8fc046e4032f4"></a>
<div class="memitem">
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          <td class="memname">#define XSCUGIC_RUN_PRIOR_OFFSET&#160;&#160;&#160;0x00000014U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Running Priority Reg. </p>

</div>
</div>
<a class="anchor" id="ga8ac1ba33bfaefe69aacd6221b0375f1c"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_RUN_PRIORITY_MASK&#160;&#160;&#160;0x000000FFU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Interrupt Priority. </p>

</div>
</div>
<a class="anchor" id="gaf8413fc164b51c233c05c6e48fdc0bf5"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_SECURITY_OFFSET&#160;&#160;&#160;0x00000080U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Interrupt Security Register. </p>

</div>
</div>
<a class="anchor" id="gab68476cc3813858c0c809ebfb4e28c74"></a>
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          <td class="memname">#define XSCUGIC_SFI_TRIG_CPU_MASK&#160;&#160;&#160;0x00FF0000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>CPU Target list. </p>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#gad71d2f581bdc46d89f38fced53e506bf">XScuGic_SoftwareIntr()</a>.</p>

</div>
</div>
<a class="anchor" id="ga7956d8a2796ad6f92fafc49d92aa1a7d"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_SFI_TRIG_INTID_MASK&#160;&#160;&#160;0x0000000FU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Set to the INTID signaled to the CPU. </p>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#gad71d2f581bdc46d89f38fced53e506bf">XScuGic_SoftwareIntr()</a>.</p>

</div>
</div>
<a class="anchor" id="ga5152b8067164fc0208df744dd20edea4"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_SFI_TRIG_OFFSET&#160;&#160;&#160;0x00000F00U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Software Triggered Interrupt Register. </p>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#gad71d2f581bdc46d89f38fced53e506bf">XScuGic_SoftwareIntr()</a>.</p>

</div>
</div>
<a class="anchor" id="ga14c75b6deed6c34d98453d802627a26e"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XSCUGIC_SFI_TRIG_SATT_MASK&#160;&#160;&#160;0x00008000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>0= Use a secure interrupt </p>

</div>
</div>
<a class="anchor" id="ga57d7eef981cdc87055eb0df1d147a822"></a>
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        <tr>
          <td class="memname">#define XSCUGIC_SFI_TRIG_TRGFILT_MASK&#160;&#160;&#160;0x03000000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Target List filter b00-Use the target List b01-All CPUs except requester b10-To Requester b11-reserved. </p>

</div>
</div>
<a class="anchor" id="gaf6958ba672ad449aa981f7fae9412455"></a>
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          <td class="memname">#define XSCUGIC_SPI_CPU0_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>CPU 0 Mask. </p>

</div>
</div>
<a class="anchor" id="ga5acd0af7b918d410b4c95853f7b8c959"></a>
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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_SPI_CPU1_MASK&#160;&#160;&#160;0x00000002U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>CPU 1 Mask. </p>

</div>
</div>
<a class="anchor" id="ga8602b97c00f48225e1d7cc8d7ed5a7bb"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_SPI_CPU2_MASK&#160;&#160;&#160;0x00000003U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>CPU 2 Mask. </p>

</div>
</div>
<a class="anchor" id="gaa32beb32b38ed8d081dab55658db505b"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_SPI_CPU3_MASK&#160;&#160;&#160;0x00000008U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>CPU 3 Mask. </p>

</div>
</div>
<a class="anchor" id="ga8fc98206cf989c81b171719c0f590676"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_SPI_CPU4_MASK&#160;&#160;&#160;0x00000010U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>CPU 4 Mask. </p>

</div>
</div>
<a class="anchor" id="gae004cb0d1b4d0f54646a1576c1054c43"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_SPI_CPU5_MASK&#160;&#160;&#160;0x00000020U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>CPU 5 Mask. </p>

</div>
</div>
<a class="anchor" id="ga95ff6c51df6995c41ec8c8a4c2104cbd"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_SPI_CPU6_MASK&#160;&#160;&#160;0x00000040U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>CPU 6 Mask. </p>

</div>
</div>
<a class="anchor" id="gade96daa17197385ab3071b1f46591d93"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_SPI_CPU7_MASK&#160;&#160;&#160;0x00000080U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>CPU 7 Mask. </p>

</div>
</div>
<a class="anchor" id="ga06ee88cda2455e25cd6c1d5b4d7eb7b3"></a>
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<div class="memproto">
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          <td class="memname">#define XSCUGIC_SPI_N_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>Each bit corresponds to an SPI input. </p>

</div>
</div>
<a class="anchor" id="ga809581b2c56e40481e49ba23535c4d52"></a>
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<div class="memproto">
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          <td class="memname">#define XSCUGIC_SPI_STAT_OFFSET&#160;&#160;&#160;0x00000D04U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>SPI Status Register 0xd04-0xd7C. </p>

</div>
</div>
<a class="anchor" id="ga0ff09d2f6f8b9b89f847f756ee0ed408"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_SPI_TARGET_OFFSET&#160;&#160;&#160;0x00000800U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8h.html">xscugic_hw.h</a>&gt;</code></p>

<p>SPI Target Register 0x800-0x8FB. </p>

</div>
</div>
<h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="gaf8e0bfe31c0fa2ca654c36715a3c13f8"></a>
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          <td class="memname">s32 XScuGic_CfgInitialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> *&#160;</td>
          <td class="paramname"><em>ConfigPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>EffectiveAddr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic_8c.html">xscugic.c</a>&gt;</code></p>

<p>CfgInitialize a specific interrupt controller instance/driver. </p>
<p>The initialization entails:</p>
<ul>
<li>Initialize fields of the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> structure</li>
<li>Initial vector table with stub function calls</li>
<li>All interrupt sources are disabled</li>
</ul>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance. </td></tr>
    <tr><td class="paramname">ConfigPtr</td><td>is a pointer to a config table for the particular device this driver is associated with. </td></tr>
    <tr><td class="paramname">EffectiveAddr</td><td>is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use Config-&gt;BaseAddress for this parameters, passing the physical address instead.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if initialization was successful</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_scu_gic.html#a231f58b4755a1856bbe3120370e5889e">XScuGic::Config</a>, <a class="el" href="struct_x_scu_gic___config.html#a7ea39fc648dff09faa2a238e9a054089">XScuGic_Config::HandlerTable</a>, and <a class="el" href="struct_x_scu_gic.html#a797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>.</p>

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          <td class="memname">s32 XScuGic_Connect </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">Xil_InterruptHandler&#160;</td>
          <td class="paramname"><em>Handler</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>CallBackRef</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic_8c.html">xscugic.c</a>&gt;</code></p>

<p>Makes the connection between the Int_Id of the interrupt source and the associated handler that is to run when the interrupt is recognized. </p>
<p>The argument provided in this call as the Callbackref is used as the argument for the handler when it is called.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance. </td></tr>
    <tr><td class="paramname">Int_Id</td><td>contains the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 </td></tr>
    <tr><td class="paramname">Handler</td><td>to the handler for that interrupt. </td></tr>
    <tr><td class="paramname">CallBackRef</td><td>is the callback reference, usually the instance pointer of the connecting driver.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<ul>
<li>XST_SUCCESS if the handler was connected correctly.</li>
</ul>
<dl class="section note"><dt>Note</dt><dd></dd></dl>
<p>WARNING: The handler provided as an argument will overwrite any handler that was previously connected. </p>

<p>References <a class="el" href="struct_x_scu_gic.html#a231f58b4755a1856bbe3120370e5889e">XScuGic::Config</a>, <a class="el" href="struct_x_scu_gic___config.html#a7ea39fc648dff09faa2a238e9a054089">XScuGic_Config::HandlerTable</a>, and <a class="el" href="struct_x_scu_gic.html#a797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>.</p>

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          <td class="memname">s32 XScuGic_DeviceInitialize </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8c.html">xscugic_hw.c</a>&gt;</code></p>

<p>CfgInitialize a specific interrupt controller instance/driver. </p>
<p>The initialization entails:</p>
<ul>
<li>Initialize fields of the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> structure</li>
<li>Initial vector table with stub function calls</li>
<li>All interrupt sources are disabled</li>
</ul>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">ConfigPtr</td><td>is a pointer to a config table for the particular device this driver is associated with. </td></tr>
    <tr><td class="paramname">EffectiveAddr</td><td>is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use Config-&gt;BaseAddress for this parameters, passing the physical address instead.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<ul>
<li>XST_SUCCESS if initialization was successful</li>
</ul>
<dl class="section note"><dt>Note</dt><dd></dd></dl>
<p>None. </p>

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          <td class="memname">void XScuGic_DeviceInterruptHandler </td>
          <td>(</td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic__hw_8c.html">xscugic_hw.c</a>&gt;</code></p>

<p>This function is the primary interrupt handler for the driver. </p>
<p>It must be connected to the interrupt source such that it is called when an interrupt of the interrupt controller is active. It will resolve which interrupts are active and enabled and call the appropriate interrupt handler. It uses the Interrupt Type information to determine when to acknowledge the interrupt.Highest priority interrupts are serviced first.</p>
<p>This function assumes that an interrupt vector table has been previously initialized. It does not verify that entries in the table are valid before calling an interrupt handler.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>is the unique identifier for the ScuGic device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_scu_gic___config.html#a0766a78c836a58b4eed2543799abaebc">XScuGic_Config::CpuBaseAddress</a>, <a class="el" href="struct_x_scu_gic___config.html#a7ea39fc648dff09faa2a238e9a054089">XScuGic_Config::HandlerTable</a>, <a class="el" href="group__scugic__v3__1.html#gad9945cea79930d883f977fc97e1aa292">XSCUGIC_ACK_INTID_MASK</a>, <a class="el" href="group__scugic__v3__1.html#gaa65c329712b1a7f3ab12b0bf4ada058d">XSCUGIC_EOI_OFFSET</a>, <a class="el" href="group__scugic__v3__1.html#ga5f1418c8f0e05b7f928c2fff42b4514d">XSCUGIC_INT_ACK_OFFSET</a>, <a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>, and <a class="el" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a>.</p>

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          <td class="memname">void XScuGic_Disable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xscugic_8c.html">xscugic.c</a>&gt;</code></p>

<p>Disables the interrupt source provided as the argument Int_Id such that the interrupt controller will not cause interrupts for the specified Int_Id. </p>
<p>The interrupt controller will continue to hold an interrupt condition for the Int_Id, but will not cause an interrupt.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance. </td></tr>
    <tr><td class="paramname">Int_Id</td><td>contains the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_scu_gic.html#a797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>, <a class="el" href="group__scugic__v3__1.html#ga7a61a9bf8e0b229925a5ddbf763b414b">XSCUGIC_DISABLE_OFFSET</a>, and <a class="el" href="group__scugic__v3__1.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>.</p>

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          <td class="memname">void XScuGic_Disconnect </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xscugic_8c.html">xscugic.c</a>&gt;</code></p>

<p>Updates the interrupt table with the Null Handler and NULL arguments at the location pointed at by the Int_Id. </p>
<p>This effectively disconnects that interrupt source from any handler. The interrupt is disabled also.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Int_Id</td><td>contains the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_scu_gic.html#a231f58b4755a1856bbe3120370e5889e">XScuGic::Config</a>, <a class="el" href="struct_x_scu_gic___config.html#a7ea39fc648dff09faa2a238e9a054089">XScuGic_Config::HandlerTable</a>, <a class="el" href="struct_x_scu_gic.html#a797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>, <a class="el" href="group__scugic__v3__1.html#ga7a61a9bf8e0b229925a5ddbf763b414b">XSCUGIC_DISABLE_OFFSET</a>, and <a class="el" href="group__scugic__v3__1.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>.</p>

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          <td class="memname">void XScuGic_Enable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xscugic_8c.html">xscugic.c</a>&gt;</code></p>

<p>Enables the interrupt source provided as the argument Int_Id. </p>
<p>Any pending interrupt condition for the specified Int_Id will occur after this function is called.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance. </td></tr>
    <tr><td class="paramname">Int_Id</td><td>contains the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_scu_gic.html#a797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>, <a class="el" href="group__scugic__v3__1.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>, and <a class="el" href="group__scugic__v3__1.html#ga7e39be0cb9e08f4c9231f76e685a76cc">XSCUGIC_ENABLE_SET_OFFSET</a>.</p>

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          <td class="memname">void XScuGic_GetPriorityTriggerType </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Priority</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Trigger</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xscugic_8c.html">xscugic.c</a>&gt;</code></p>

<p>Gets the interrupt priority and trigger type for the specificd IRQ source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the instance to be worked on. </td></tr>
    <tr><td class="paramname">Int_Id</td><td>is the IRQ source number to modify </td></tr>
    <tr><td class="paramname">Priority</td><td>is a pointer to the value of the priority of the IRQ source. This is a return value. </td></tr>
    <tr><td class="paramname">Trigger</td><td>is pointer to the value of the trigger of the IRQ source. This is a return value.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p>References <a class="el" href="struct_x_scu_gic.html#a797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>, <a class="el" href="group__scugic__v3__1.html#ga3d639fe1851f9d833367fb4322390eeb">XScuGic_DistReadReg</a>, <a class="el" href="xscugic__hw_8h.html#a3921ef6af4f5fd6a35cb5089ef85a22a">XSCUGIC_INT_CFG_OFFSET_CALC</a>, <a class="el" href="group__scugic__v3__1.html#gaf56426a8af8b676cb9184cf2196b6bf4">XSCUGIC_PRIORITY_MASK</a>, and <a class="el" href="xscugic__hw_8h.html#af5f397349cab91733882c9d388498d5b">XSCUGIC_PRIORITY_OFFSET_CALC</a>.</p>

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          <td class="memname">void XScuGic_GetPriTrigTypeByDistAddr </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>DistBaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Priority</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Trigger</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xscugic__hw_8c.html">xscugic_hw.c</a>&gt;</code></p>

<p>Gets the interrupt priority and trigger type for the specificd IRQ source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddr</td><td>is the device base address </td></tr>
    <tr><td class="paramname">Int_Id</td><td>is the IRQ source number to modify </td></tr>
    <tr><td class="paramname">Priority</td><td>is a pointer to the value of the priority of the IRQ source. This is a return value. </td></tr>
    <tr><td class="paramname">Trigger</td><td>is pointer to the value of the trigger of the IRQ source. This is a return value.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This API has the similar functionality of XScuGic_GetPriority TriggerType() and should be used when there is no InstancePtr. </dd></dl>

<p>References <a class="el" href="xscugic__hw_8h.html#a3921ef6af4f5fd6a35cb5089ef85a22a">XSCUGIC_INT_CFG_OFFSET_CALC</a>, <a class="el" href="group__scugic__v3__1.html#gaf56426a8af8b676cb9184cf2196b6bf4">XSCUGIC_PRIORITY_MASK</a>, <a class="el" href="xscugic__hw_8h.html#af5f397349cab91733882c9d388498d5b">XSCUGIC_PRIORITY_OFFSET_CALC</a>, and <a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>.</p>

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          <td class="memname">void XScuGic_InterruptHandler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p><code>#include &lt;<a class="el" href="xscugic_8h.html">xscugic.h</a>&gt;</code></p>

<p>This function is the primary interrupt handler for the driver. </p>
<p>It must be connected to the interrupt source such that it is called when an interrupt of the interrupt controller is active. It will resolve which interrupts are active and enabled and call the appropriate interrupt handler. It uses the Interrupt Type information to determine when to acknowledge the interrupt. Highest priority interrupts are serviced first.</p>
<p>This function assumes that an interrupt vector table has been previously initialized. It does not verify that entries in the table are valid before calling an interrupt handler.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_scu_gic.html#a231f58b4755a1856bbe3120370e5889e">XScuGic::Config</a>, <a class="el" href="struct_x_scu_gic___config.html#a7ea39fc648dff09faa2a238e9a054089">XScuGic_Config::HandlerTable</a>, <a class="el" href="group__scugic__v3__1.html#gad9945cea79930d883f977fc97e1aa292">XSCUGIC_ACK_INTID_MASK</a>, <a class="el" href="group__scugic__v3__1.html#ga2f3bba7c5247812158ef4fde7a0e7dfe">XScuGic_CPUReadReg</a>, <a class="el" href="group__scugic__v3__1.html#ga2a4ba236ff7bfeab20b5ca81082f2b13">XScuGic_CPUWriteReg</a>, <a class="el" href="group__scugic__v3__1.html#gaa65c329712b1a7f3ab12b0bf4ada058d">XSCUGIC_EOI_OFFSET</a>, and <a class="el" href="group__scugic__v3__1.html#ga5f1418c8f0e05b7f928c2fff42b4514d">XSCUGIC_INT_ACK_OFFSET</a>.</p>

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          <td class="memname">void XScuGic_InterruptMaptoCpu </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Cpu_Id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xscugic_8c.html">xscugic.c</a>&gt;</code></p>

<p>Sets the target CPU for the interrupt of a peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the instance to be worked on. </td></tr>
    <tr><td class="paramname">Cpu_Id</td><td>is a CPU number for which the interrupt has to be targeted </td></tr>
    <tr><td class="paramname">Int_Id</td><td>is the IRQ source number to modify</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p>References <a class="el" href="group__scugic__v3__1.html#ga3d639fe1851f9d833367fb4322390eeb">XScuGic_DistReadReg</a>, <a class="el" href="group__scugic__v3__1.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>, and <a class="el" href="xscugic__hw_8h.html#aa2cf2e3acd2e8cf537c415276efa3a97">XSCUGIC_SPI_TARGET_OFFSET_CALC</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> * XScuGic_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
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<p><code>#include &lt;<a class="el" href="xscugic_8h.html">xscugic.h</a>&gt;</code></p>

<p>Looks up the device configuration based on the unique device ID. </p>
<p>A table contains the configuration info for each device in the system.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>is the unique identifier for a device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>A pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> configuration structure for the specified device, or NULL if the device was not found.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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          <td class="memname">void XScuGic_RegisterHandler </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>BaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">s32&#160;</td>
          <td class="paramname"><em>InterruptID</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">Xil_InterruptHandler&#160;</td>
          <td class="paramname"><em>IntrHandler</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>CallBackRef</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xscugic__hw_8c.html">xscugic_hw.c</a>&gt;</code></p>

<p>Register a handler function for a specific interrupt ID. </p>
<p>The vector table of the interrupt controller is updated, overwriting any previous handler. The handler function will be called when an interrupt occurs for the given interrupt ID.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the CPU Interface Register base address of the interrupt controller whose vector table will be modified. </td></tr>
    <tr><td class="paramname">InterruptId</td><td>is the interrupt ID to be associated with the input handler. </td></tr>
    <tr><td class="paramname">Handler</td><td>is the function pointer that will be added to the vector table for the given interrupt ID. </td></tr>
    <tr><td class="paramname">CallBackRef</td><td>is the argument that will be passed to the new handler function when it is called. This is user-specific.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd></dd></dl>
<p>Note that this function has no effect if the input base address is invalid. </p>

<p>References <a class="el" href="struct_x_scu_gic___config.html#a7ea39fc648dff09faa2a238e9a054089">XScuGic_Config::HandlerTable</a>.</p>

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          <td class="memname">s32 XScuGic_SelfTest </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xscugic_8h.html">xscugic.h</a>&gt;</code></p>

<p>Run a self-test on the driver/device. </p>
<p>This test reads the ID registers and compares them.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<ul>
<li>XST_SUCCESS if self-test is successful.</li>
<li>XST_FAILURE if the self-test is not successful.</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_scu_gic.html#a797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>, <a class="el" href="group__scugic__v3__1.html#ga3d639fe1851f9d833367fb4322390eeb">XScuGic_DistReadReg</a>, and <a class="el" href="group__scugic__v3__1.html#ga41becddbff3dcc589f4c9d70d0177ff6">XSCUGIC_PCELLID_OFFSET</a>.</p>

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          <td class="memname">void XScuGic_SetPriorityTriggerType </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Priority</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Trigger</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p><code>#include &lt;<a class="el" href="xscugic_8c.html">xscugic.c</a>&gt;</code></p>

<p>Sets the interrupt priority and trigger type for the specificd IRQ source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the instance to be worked on. </td></tr>
    <tr><td class="paramname">Int_Id</td><td>is the IRQ source number to modify </td></tr>
    <tr><td class="paramname">Priority</td><td>is the new priority for the IRQ source. 0 is highest priority, 0xF8 (248) is lowest. There are 32 priority levels supported with a step of 8. Hence the supported priorities are 0, 8, 16, 32, 40 ..., 248. </td></tr>
    <tr><td class="paramname">Trigger</td><td>is the new trigger type for the IRQ source. Each bit pair describes the configuration for an INT_ID. SFI Read Only b10 always PPI Read Only depending on how the PPIs are configured. b01 Active HIGH level sensitive b11 Rising edge sensitive SPI LSB is read only. b01 Active HIGH level sensitive b11 Rising edge sensitive/</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_scu_gic.html#a797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>, <a class="el" href="group__scugic__v3__1.html#ga3d639fe1851f9d833367fb4322390eeb">XScuGic_DistReadReg</a>, <a class="el" href="group__scugic__v3__1.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>, <a class="el" href="xscugic__hw_8h.html#a3921ef6af4f5fd6a35cb5089ef85a22a">XSCUGIC_INT_CFG_OFFSET_CALC</a>, <a class="el" href="group__scugic__v3__1.html#gaf56426a8af8b676cb9184cf2196b6bf4">XSCUGIC_PRIORITY_MASK</a>, and <a class="el" href="xscugic__hw_8h.html#af5f397349cab91733882c9d388498d5b">XSCUGIC_PRIORITY_OFFSET_CALC</a>.</p>

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          <td class="memname">void XScuGic_SetPriTrigTypeByDistAddr </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>DistBaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Priority</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Trigger</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xscugic__hw_8c.html">xscugic_hw.c</a>&gt;</code></p>

<p>Sets the interrupt priority and trigger type for the specificd IRQ source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddr</td><td>is the device base address </td></tr>
    <tr><td class="paramname">Int_Id</td><td>is the IRQ source number to modify </td></tr>
    <tr><td class="paramname">Priority</td><td>is the new priority for the IRQ source. 0 is highest priority, 0xF8 (248) is lowest. There are 32 priority levels supported with a step of 8. Hence the supported priorities are 0, 8, 16, 32, 40 ..., 248. </td></tr>
    <tr><td class="paramname">Trigger</td><td>is the new trigger type for the IRQ source. Each bit pair describes the configuration for an INT_ID. SFI Read Only b10 always PPI Read Only depending on how the PPIs are configured. b01 Active HIGH level sensitive b11 Rising edge sensitive SPI LSB is read only. b01 Active HIGH level sensitive b11 Rising edge sensitive/</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This API has the similar functionality of XScuGic_SetPriority TriggerType() and should be used when there is no InstancePtr. </dd></dl>

<p>References <a class="el" href="xscugic__hw_8h.html#a3921ef6af4f5fd6a35cb5089ef85a22a">XSCUGIC_INT_CFG_OFFSET_CALC</a>, <a class="el" href="group__scugic__v3__1.html#gaf56426a8af8b676cb9184cf2196b6bf4">XSCUGIC_PRIORITY_MASK</a>, <a class="el" href="xscugic__hw_8h.html#af5f397349cab91733882c9d388498d5b">XSCUGIC_PRIORITY_OFFSET_CALC</a>, <a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>, and <a class="el" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a>.</p>

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          <td class="memname">s32 XScuGic_SoftwareIntr </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Cpu_Id</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p><code>#include &lt;<a class="el" href="xscugic_8c.html">xscugic.c</a>&gt;</code></p>

<p>Allows software to simulate an interrupt in the interrupt controller. </p>
<p>This function will only be successful when the interrupt controller has been started in simulation mode. A simulated interrupt allows the interrupt controller to be tested without any device to drive an interrupt input signal into it.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance. </td></tr>
    <tr><td class="paramname">Int_Id</td><td>is the software interrupt ID to simulate an interrupt. </td></tr>
    <tr><td class="paramname">Cpu_Id</td><td>is the list of CPUs to send the interrupt.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<p>XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be simulated</p>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_scu_gic.html#a797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>, <a class="el" href="group__scugic__v3__1.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>, <a class="el" href="group__scugic__v3__1.html#gab68476cc3813858c0c809ebfb4e28c74">XSCUGIC_SFI_TRIG_CPU_MASK</a>, <a class="el" href="group__scugic__v3__1.html#ga7956d8a2796ad6f92fafc49d92aa1a7d">XSCUGIC_SFI_TRIG_INTID_MASK</a>, and <a class="el" href="group__scugic__v3__1.html#ga5152b8067164fc0208df744dd20edea4">XSCUGIC_SFI_TRIG_OFFSET</a>.</p>

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<h2 class="groupheader">Variable Documentation</h2>
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          <td class="memname"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> XScuGic_ConfigTable[XPAR_SCUGIC_NUM_INSTANCES]</td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xscugic__sinit_8c.html">xscugic_sinit.c</a>&gt;</code></p>

<p>This table contains configuration information for each GIC device in the system. </p>
<p>The <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> driver must know when to acknowledge the interrupt. The entry which specifies this as a bit mask where each bit corresponds to a specific interrupt. A bit set indicates to ACK it before servicing it. Generally, acknowledge before service is used when the interrupt signal is edge-sensitive, and after when the signal is level-sensitive.</p>
<p>Refer to the <a class="el" href="struct_x_scu_gic___config.html" title="This typedef contains configuration information for the device. ">XScuGic_Config</a> data structure in <a class="el" href="xscugic_8h.html">xscugic.h</a> for details on how this table should be initialized. </p>

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          <td class="memname"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES]</td>
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<p><code>#include &lt;<a class="el" href="xscugic__g_8c.html">xscugic_g.c</a>&gt;</code></p>
<b>Initial value:</b><div class="fragment"><div class="line">=</div>
<div class="line">{</div>
<div class="line">    {</div>
<div class="line">        (u16)XPAR_SCUGIC_0_DEVICE_ID,   </div>
<div class="line">        (u32)XPAR_SCUGIC_0_CPU_BASEADDR,        </div>
<div class="line">        (u32)XPAR_SCUGIC_0_DIST_BASEADDR        </div>
<div class="line">    }</div>
<div class="line">}</div>
</div><!-- fragment -->
<p>This table contains configuration information for each GIC device in the system. </p>
<p>The <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> driver must know when to acknowledge the interrupt. The entry which specifies this as a bit mask where each bit corresponds to a specific interrupt. A bit set indicates to ACK it before servicing it. Generally, acknowledge before service is used when the interrupt signal is edge-sensitive, and after when the signal is level-sensitive.</p>
<p>Refer to the <a class="el" href="struct_x_scu_gic___config.html" title="This typedef contains configuration information for the device. ">XScuGic_Config</a> data structure in <a class="el" href="xscugic_8h.html">xscugic.h</a> for details on how this table should be initialized. </p>

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          <td class="memname"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES]</td>
        </tr>
      </table>
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<p><code>#include &lt;<a class="el" href="xscugic__hw_8c.html">xscugic_hw.c</a>&gt;</code></p>

<p>This table contains configuration information for each GIC device in the system. </p>
<p>The <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> driver must know when to acknowledge the interrupt. The entry which specifies this as a bit mask where each bit corresponds to a specific interrupt. A bit set indicates to ACK it before servicing it. Generally, acknowledge before service is used when the interrupt signal is edge-sensitive, and after when the signal is level-sensitive.</p>
<p>Refer to the <a class="el" href="struct_x_scu_gic___config.html" title="This typedef contains configuration information for the device. ">XScuGic_Config</a> data structure in <a class="el" href="xscugic_8h.html">xscugic.h</a> for details on how this table should be initialized. </p>

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